Multi-core shared page miss handler

ABSTRACT

Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present patent application is a continuation application claiming priority from U.S. patent application Ser. No. 13/191,294 filed Jul. 26, 2011, and titled: “Multi-Core Shared Page Miss Handler”, which is incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

This disclosure relates generally to the fields of computing and/or communications. In particular, the disclosure relates to a shared page miss handler for use by multiple processing cores or other devices in a multi-core system.

BACKGROUND OF THE DISCLOSURE

Modern processors often include caches to improve the performance of accessing external memory by providing copies of instructions and/or data in smaller faster memories with shorter access latencies. In addition such caches may provide support for fast virtual to physical address translations using a device such as a translation lookaside buffer (TLB) to cache virtual to physical address translations, for example from the system page tables in a paged virtual memory system. When a TLB matches a virtual address to one of the translations stored in the TLB, we may refer to such and event as a TLB hit and the retrieved physical address can be used to access memory in a cache or in main memory more quickly. When a TLB fails to match a virtual address to one of the translations stored in the TLB, we may refer to such and event as a TLB miss or a page miss, and the translation proceeds by looking up the corresponding page table in a process called a page walk.

A page walk is an expensive process, as it involves reading the contents of multiple memory locations and using them to compute the physical address. Modern processors often include a page-miss handler (PMH) in hardware to perform the page walk more quickly. After the physical address is determined by the page walk, the virtual address to physical address mapping is entered into the TLB to be reused in subsequent accesses.

In a multi-core system with multiple processing cores, each of the multiple processing cores may include such a PMH to facilitate page walks on page misses and to populate their respective TLB. In this disclosure, we may refer to a core or processing core in contrast to a thread or execution thread. The processing core may include support for multiple execution threads, including for example, a per-thread general-purpose register file, a per-thread floating-point register file, per-thread execution queues, per-thread state information storage, and partitionalble cache or caches and TLB storage.

In a multi-core system with multiple processing cores, certain other processing hardware or devices may also access the systems main memory. A graphics processor, for example, may read and write to buffers in memory at locations provided by a central processing core or cores. In some systems it may also be desirable for a graphics processor to access a shared cache along with the central processing core or cores to improve access times. In such systems it may even be desirable to provide a device, such as a graphics processor or video processor, etc., with a TLB to cache virtual to physical address translations, and a PMH to facilitate page walks on page misses and to populate their respective TLB.

As the number of processing cores and other devices accessing caches or using virtual memory increases, there may be good reason to expect problems, such as additional memory congestion, and conflicts, and duplication of page walks when virtual memory space is shared by more of these devices.

To date, potential solutions to such reasonably expected problems have not been adequately explored.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings.

FIG. 1 illustrates a prior art technique for sharing virtual memory in a multi-core system.

FIG. 2 illustrates one embodiment of an apparatus for using a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

FIG. 3 illustrates a flow diagram for one embodiment of a process to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

FIG. 4 illustrates a flow diagram for an alternative embodiment of a process to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

FIG. 5 illustrates one embodiment of a processor that utilizes a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

FIG. 6 illustrates one embodiment of a system that utilizes a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

DETAILED DESCRIPTION

Methods and apparatus are disclosed herein for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices. A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

These and other embodiments of the present invention may be realized in accordance with the following teachings and it should be evident that various modifications and changes may be made in the following teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims and their equivalents.

FIG. 1 illustrates a prior art technique for sharing virtual memory in a multi-core system. A multi-core processor or multi-core processing system may have various multiple processor cores or other processing devices. For example, the system of FIG. 1 has some number of processor cores, two of which are shown as core 102 and core 104, together with one or more graphics processors, such as GFX 106 or other processors, say for example, device 109. Core 102 and core 104 may be multi-threaded cores processing multiple process threads for execution via decode 131 and decode 151, per-thread queues 133 and 153, floating point/single-instruction multiple-data registers FP/SIMD REGS 135 a and FP/SIMD REGS 155 a, general registers GEN REGS 135 b and GEN REGS 155 b, floating point/single-instruction multiple-data execution units FP/SIMD EXU 137 a and FP/SIMD EXU 157 a, and integer execution units INT EXU 137 b and INT EXU 157 b, respectively. Core 102 and core 104 may also be coupled with external physical memory (not shown) via a bus/interconnect 115 and memory units MEM-U 125 and MEM-U 145 through bus/interconnect units B/I-U 120 and B/I-U 140, respectively. Core 102 and core 104 may also be coupled with other processing devices GFX 106 and device 109 via external physical memory and bus/interconnect 115 and optionally last level cache, LLC 114.

These multiple processor cores and other processing devices may share virtual memory address spaces via external physical memory and optionally through last level cache, LLC 116. Typically, the homogeneous processor cores may have cache hierachies, e.g. I-cache 123, D-cache 124, L2 126 and I-cache 143, D-cache 144, L2 146, respectively; and TLBs, e.g. I-TLB 121, D-TLB 122 and I-TLB 141, D-TLB 142, respectively to cache virtual to physical address translations from the system page tables in a paged virtual memory system.

The homogeneous processor cores 102 and 104 may also include page-miss handlers, PMH 130 and PMH 150, in hardware to perform page walks through system page tables. When one of the processor cores 102 and 104 tries to access a page in virtual memory that is not mapped to anything in physical memory, or that is not accessible because of the settings of its access rights, the memory access will cause a page fault, and the operating system will be invoked to “fix” the problem.

The other processing devices, such as graphics processor, GFX 106, and device 109 may also have mechanisms such as TLBs for performing virtual to physical address translations, but typically there is some software that runs on the processor cores 102 and 104 and may communicate with drivers for the processing devices GFX 106 and device 109 to set up page tables, etc. for some limited sharing of the paged virtual memory system with the processing devices GFX 106 and device 109. But unlike in the processor cores 102 and 104, these mechanisms may have limited capabilities, lacking the ability to handle page faults, for example. Therefore the pages that are shared with these other processing devices may need to be locked down in physical memory, preventing the operating system from paging them in from, and out to disk as demand dictates. Thus the number of applications that can be supported may be limited, or the amount of physical memory required may be greater than it would otherwise have been. Further the software that runs on the processor cores 102 or 104 to set up page tables, etc. for sharing paged virtual memory with the other processing devices GFX 106 and device 109 incurs a performance overhead, which may reduce the effectiveness of using processing devices GFX 106 and device 109.

In such a multi-core system with multiple processing cores, the other processing devices GFX 106 and device 109 may also access the system's main memory. In some systems it may also be desirable for graphics processor GFX 106 to access a shared cache along with the central processing cores 102 or 104 to improve access times. In such systems it may even be desirable to provide a device, such as processing devices GFX 106 and device 109, with a TLB to cache virtual to physical address translations, and a PMH to facilitate page walks on page misses and to populate their respective TLB.

It will be appreciated that as the number of processing cores and other devices accessing caches or using virtual memory increases, there may be good reason to expect problems, such as additional memory congestion, and conflicts, and duplication of page walks when virtual memory space is shared by more of these devices.

FIG. 2 illustrates one embodiment of an apparatus 201 for using a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

Apparatus 201 comprises TLB 212 to store virtual address translation entries. Page-miss handler, PMH 210, is coupled with the TLB 212 to to facilitate page walks on page misses and to populate virtual address translation entries of TLB 212. For the sake of illustration TLB 212 and PMH 210 are shown as being included in apparatus 201 but it will be appreciated that portions of one or both may be implemented as a separate or a distributed hardware and/or software data structures and reside outside of apparatus 201, for example including main memory.

Apparatus 201 optionally comprises also last level cache, LLC 214, and which are shown as being included in apparatus 201 but may be implemented as separate hardware or software and may reside outside of apparatus 201.

Apparatus 201 is operatively coupled with bus/interconnect 215 for communicating with a multi-core processor or multi-core processing system having multiple processor cores or other processing devices, for sharing virtual memory in the multi-core system. The system may include multiple processor cores, two of which are shown as core 202 and core 204, as well as other processing devices such as graphics devices, two of which are shown as GFX 206 and GFX 208, and optionally other processing devices such as video device 207 and device 209.

The multiple processor cores 202 and 204 may be multi-threaded cores processing multiple process threads for execution via decode 231 and decode 251, per-thread queues 233 and 253, floating point/single-instruction multiple-data registers FP/SIMD REGS 235 a and FP/SIMD REGS 255 a, general registers GEN REGS 235 b and GEN REGS 255 b, floating point/single-instruction multiple-data execution units FP/SIMD EXU 237 a and FP/SIMD EXU 257 a, and integer execution units INT EXU 237 b and INT EXU 257 b, respectively. Core 202 and core 204 may also be coupled with external memory (not shown) via a bus/interconnect 215 and memory units MEM-U 225 and MEM-U 245 through bus/interconnect units B/I-U 220 and B/I-U 240, respectively. Core 202 and core 204 may also be coupled with graphics processing devices GFX 206 and GFX 208, and optionally other heterogeneous processing devices such as video device 207 and device 209 via external memory and bus/interconnect 215, and optionally via last level cache, LLC 214.

These multiple processing cores or other processing devices may share virtual memory address spaces via external physical memory and optionally through last level cache, LLC 116. Typically, the processor cores 202 and 204 may have cache hierachies, e.g. I-cache 223, D-cache 224, L2 226 and I-cache 243, D-cache 244, L2 246, respectively; and TLBs, e.g. I-TLB 221, D-TLB 222 and I-TLB 241, D-TLB 242, respectively to cache virtual to physical address translations from the system page tables in a paged virtual memory system.

The graphics processors, GFX 206 and GFX 208, and optionally other processing devices such as video device 207 and device 209 may also have mechanisms such as TLBs, e.g. TLB 262, TLB 282, TLB 272 and TLB 292, respectively, for performing virtual to physical address translations. Various embodiments of TLB 262, TLB 282, TLB 272 and TLB 292, respectively, may or may not have the same capabilities, or capabilities comparable to homogeneous processor cores 202 and 204. The graphics processing devices GFX 206, GFX 208, and optionally video device 207 and device 209 may also have caches, e.g. cache 264, cache 284, cache 274 and cache 294, respectively.

If one or more of processor cores 202 and 204, graphics processing devices GFX 206, GFX 208, and optionally video device 207 and device 209, while accessing their TLBs via a TLB lookup, generate a page miss, then they may send a page miss requests to the central PMH 210 of apparatus 201. Apparatus 201 may receive one or more page miss requests, e.g. in a page miss request queue, from one or more respective requesting devices of the plurality of devices, processor cores 202 and 204, graphics processing devices GFX 206, GFX 208, and optionally video device 207 and device 209, in the multi-core system. When processing a page miss request from one of the requesting devices, apparatus 201 may include arbitration logic in order to arbitrate and identify which page miss request of the one or more requesting devices to process. Apparatus 201 may perform a second local TLB lookup to TLB 212 to satisfy the page miss request and upon a page miss in TLB 212, apparatus 201 may then perform a page table walk using PMH 210 to generate a physical address responsive to the first page miss request. Then the physical address is sent by communication logic of apparatus 201 to the corresponding requesting device, or a fault is signaled by apparatus 201 to an operating system for the corresponding requesting device responsive to the first page miss request. It will be appreciated that whenever duplicate page miss request are received by apparatus 201, if any duplicate request has been, or is being processed by PMH 210, the other duplicate requests can wait to be satisfied along with the first request. Thus duplication of page walks may be eliminated by the PMH page walk duplication logic of apparatus 201 when virtual memory space is shared by more of these devices. Similarly, if the first request generates a page fault due to a page not being present in physical memory, duplicate page fault signals to the operating system for the same reason may be eliminated by the PMH page fault duplication logic of apparatus 201, while page faults for access rights violations may be preserved but without a duplication of the page walk.

Embodiments of one or more processes to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system will also be described in greater detail below, in particular with reference to FIGS. 3-4.

FIG. 3 illustrates a flow diagram for one embodiment of a process 301 to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system. Process 301 and other processes herein disclosed are performed by processing blocks that may comprise dedicated hardware or software or firmware operation codes executable by general purpose machines or by special purpose machines or by a combination of both.

In processing block 340 of process 301, one or more page miss requests is received from one or more respective requesting devices of a plurality of devices in the multi-core system. In processing block 350, arbitration is performed to identify a first page miss requests of the one or more requesting devices. In processing block 360, a page table walk is performed using the central PMH to generate a physical address responsive to the first page miss request. Then in processing block 370, the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

FIG. 4 illustrates a flow diagram for an alternative embodiment of a process 403 to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

In processing block 420 of process 402, one or more processing cores or other devices, e.g. processor cores 202 and 204, graphics processing devices GFX 206, GFX 208, and optionally video device 207 and device 209, are continuing execution. In processing block 421, a TLB lookup is performed by the one or more processing cores or other devices. If in one or more processing cores or other devices, while performing a TLB lookup, a page miss is generated in processing block 423, then in processing block 420 they may send a page miss requests to the central PMH, e.g. PMH 210 of apparatus 201. If not, then a physical address is returned from the TLB in processing block 425, and they may continue execution in processing block 420.

In processing block 440 of process 401, one or more page miss requests is received from one or more respective requesting devices of a plurality of devices in the multi-core system, e.g. processor cores 202 and 204, graphics processing devices GFX 206, GFX 208, and optionally video device 207 and device 209. In processing block 350, arbitration is performed until a first page miss request of the one or more requesting devices is selected. In processing block 451 a second TLB lookup, e.g. to TLB 212, is performed to satisfy the page miss request and upon a second page miss in processing block 453, i.e. in TLB 212, processing proceeds to processing block 459. Otherwise on a TLB hit, processing proceeds to processing block 455 where the page miss request is satisfied and processing resumes in processing block 427 of process 402 where the TLB entry is installed. Then a physical address is returned from the TLB in processing block 425, and execution may continue in processing block 420.

In processing block 459, following from a page miss in processing block 453, if the page miss request is a duplicate request, then in processing block 461 the request waits for the results of a prior page table walk finishing its walk. If the request is not a duplicate request, then a page table walk may be performed in processing block 460, e.g. using PMH 210, to generate a physical address responsive to the first page miss request. If the page table walk results in a fault in processing block 471, then a page fault is signaled to the operating system for the corresponding requesting device responsive to the first page miss request in processing block 473.

Otherwise in processing block 475, the physical address is returned and the TLB entry is installed in processing block 457, i.e. for TLB 212. In processing block 455 the first page miss request is satisfied and the physical address is sent to the corresponding requesting device. Then processing resumes in processing block 427 of process 402 where the TLB entry is installed (i.e. in the TLB of the requesting device). A physical address is then returned from the TLB in processing block 425, and execution may continue in processing block 420.

FIG. 5 illustrates one embodiment of a processor 505 that utilizes a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system. Apparatus 501 of processor 505 comprises TLB 512 to store virtual address translation entries. Page-miss handler, PMH 510, is coupled with the TLB 512 to facilitate page walks on page misses and to populate virtual address translation entries of TLB 512. For the sake of illustration TLB 512 and PMH 510 are shown as being included in apparatus 501 but it will be appreciated that portions of one or both may be implemented as a separate or a distributed hardware and/or software data structures and reside outside of apparatus 501, for example including main memory.

Apparatus 501 optionally comprises also last level cache, LLC 514, and which are shown as being included in apparatus 501 but may be implemented as separate hardware or software and may reside outside of apparatus 501.

Apparatus 501 is operatively coupled with busses/interconnects 515 and 551 for communicating with multi-core processor 505 or a multi-core processing system having multiple processor cores or other processing devices, for sharing virtual memory, via memory control 552 through external memory (not shown) in the multi-core system. The system may include multiple processor cores, two of which are shown as core 502 and core 504, as well as other processing devices such as graphics devices, two of which are shown as GFX 506 and GFX 508, and optionally other processing devices such as video device 507 and device 509.

The multiple processor cores 502 and 504 may be multi-threaded cores processing multiple process threads for execution as described, for example, with regard to FIG. 2. Core 502 and core 504 may be coupled with varios devices via a bus/interconnect 515, e.g. I/O expansion device 537, NAND control 557, transport processor 558, security processor 559, video display logic 527, audio/video I/O 548, audio decode logic 549, and optionally single-instruction-multiple-data (SIMD) coprocessor 591. Core 502 and core 504 may also be coupled with external memory via a bus/interconnect 551 and memory control 552. Core 502 and core 504 may also be coupled with graphics processing devices GFX 506 and GFX 508, and optionally other processing devices such as video device 507 and device 509 via external memory and bus/interconnects 515 and 551 and optionally via last level cache, LLC 514.

These multiple processing cores or other processing devices may share virtual memory address spaces via an external main memory and optionally through last level cache, LLC 514. Typically, the processor cores may have cache hierachies, and TLBs, e.g. TLB 522 and TLB 542, respectively to cache virtual to physical address translations from the system page tables in a paged virtual memory system.

The graphics processing devices, GFX 506 and GFX 508, and optionally other processing devices such as video device 507 and device 509 may also have mechanisms such as TLBs, e.g. TLB 562, TLB 582, TLB 572 and TLB 592, respectively, for performing virtual to physical address translations. Various embodiments of TLB 562, TLB 582, TLB 572 and TLB 592, respectively, may or may not have the same capabilities, or capabilities comparable to processor cores 502 and 504.

If one or more of processor cores 502 and 504, graphics processing devices GFX 506, GFX 508, and optionally video device 507 and device 509, while accessing their TLBs via a TLB lookup, generate a page miss, then they may send a page miss requests to the central PMH 510 of apparatus 501. Apparatus 501 may receive one or more page miss requests from one or more respective requesting devices of the plurality of devices, processor cores 502 and 504, graphics processing devices GFX 506, GFX 508, and optionally video device 507 and device 509, in the multi-core system by any suitable means, e.g. such as a request queue. When processing a page miss request from one of the requesting devices, apparatus 501 may employ arbitration logic to identify which page miss request of the one or more requesting devices to process. Apparatus 501 may perform a second local TLB lookup to TLB 512 to satisfy the page miss request and upon a page miss in TLB 512, apparatus 501 may then perform a page table walk using PMH 510 to generate a physical address responsive to the first page miss request. Then the physical address may be sent by communication logic of apparatus 501 to the corresponding requesting device, or a fault is signaled by apparatus 501 to an operating system for the corresponding requesting device responsive to the first page miss request. It will be appreciated that whenever duplicate page miss request are received by apparatus 501, if any duplicate request has been, or is being processed by PMH 510, PMH logic of apparatus 501 may cause the other duplicate requests to wait to be satisfied along with the first request. Thus duplication of page walks may be eliminated when virtual memory space is shared by more of these devices. Similarly, if the first request generates a page faul, page fault duplication logic of apparatus 501 may also cause duplicate page fault signals to the operating system to be eliminated.

FIG. 6 illustrates one embodiment of a system 603 that utilizes a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

System 603 includes apparatus 601 of processor 605, which comprises TLB 612 to store virtual address translation entries. Page-miss handler, PMH 610, is coupled with the TLB 612 to to facilitate page walks on page misses and to populate virtual address translation entries of TLB 612. For the sake of illustration TLB 612 and PMH 610 are shown as being included in apparatus 601 but it will be appreciated that portions of one or both may be implemented as a separate or a distributed hardware and/or software data structures and reside outside of apparatus 601, for example including main memory 655.

Apparatus 601 optionally comprises also last level cache, LLC 614, and which are shown as being included in apparatus 601 but may be implemented as separate hardware or software and may reside outside of apparatus 601.

Apparatus 601 is operatively coupled with busses/interconnects 615 and 651 for communicating with multi-core processor 605 or a multi-core processing system having multiple processor cores or other processing devices, for sharing virtual memory, via memory control 652 through external memory 655, in the multi-core system.

Embodiments of system 603 may be implemented using standard or non-standard or proprietary technologies, interfaces, busses or interconnects 615 and 651 such as the (Peripheral Component Interconnect) PCI or PCI Express or (Serial Advanced Technology Attachment) SATA for communicating with a multi-core processor or multi-core processing system.

Other embodiments of system 603 may be implemented using standard or non-standard or proprietary technologies, interfaces, busses or interconnects—for example, the SPI (Serial Peripheral Interface) bus; the ISA (Industry Standard Architecture) bus, PC/104, PC/104+—and Extended ISA; USB (Universal Serial Bus) AVC (Audio Video Class); AMBA (Advanced Microcontroller Bus Architecture) (Advanced Peripheral Bus) APB; FireWire (IEEE Std 1394a-2000 High Performance Serial Bus—Amendment 1, ISBN 0-7381-1958-X; IEEE Std 1394b-2002 High Performance Serial Bus—Amendment 2, ISBN 0-7381-3253-5; IEEE Std 1394c-2006, 2007 Jun. 8, ISBN 0-7381-5237-4); HDMI (High-Definition Multimedia Interface); the VESA's (Video Electronic Standards Association) DisplayPort and Mini DisplayPort; the MIPI® (Mobile Industry Processor Interface) Alliance's SLIMbus® (Serial Low-power Inter-chip Media Bus), LLI (Low Latency Interface), CSI (Camera Serial Interface) DSI (Display Serial Interface), etc.

System 603 may include multiple processor cores, two of which are shown as core 602 and core 604, as well as other processing devices such as graphics devices, two of which are shown as GFX 606 and GFX 608, and optionally other processing devices such as video device 607 and device 609.

The multiple processor cores 602 and 604 may be multi-threaded cores processing multiple process threads for execution. Processor core 602 and core 604 may be coupled with various devices via a bus/interconnect 615, e.g. bridge 630, wireless connectivity device 620, modem device 626, and audio I/O devices 628. Some embodiments of system 603 may be implemented as a system on a chip, for example, to use in a tablet computer or a smart phone. In such embodiments wireless connectivity device 620 may provide a wireless LAN (local area network) link, modem device 626 may provide a 4G (fourth generation), 5G (fifth generation), or later telephone link, and audio I/O devices 628 may provide a set of audio human interface devices, for example, a headset, speakers, handset microphone, audio input and output channels, and amplifiers.

Processor cores 602 and 604 are coupled with bus/interconnect 615 for communicating with various other system devices, which may include but are not limited to wireless connectivity device 620, modem device 626, and audio I/O devices 628, camera interface 621, Fast IrDA (Infrared Data Association) port 623, HD (high definition) multimedia interface 624, USB 625, display control 627, and alternate master interface 629. Processor cores 602 and 604 are also coupled with bus/interconnect 615, bridge 630 and bus/interconnect 611 for communicating with various other system devices, which may include but are not limited to flash memory 613, SD (secure digital) memory 616, MMC (multimedia card) 617 and SSD (solid state drive) 619. Processor cores 602 and 604 are coupled with bus/interconnect 615, bridge 630 and bus/interconnect 618 for communicating with various other system devices, which may include but are not limited to UART (universal asynchronous receiver/transmitter) 631, camera control 632, Blue Tooth UART 633 optionally including a Wi-Fi 802.11 a/b/g transceiver and/or a GPS (Global Positioning System) transceiver, keypad 634, battery control 635, I/O expansion 637 and touch screen control 639.

Processor core 602 and core 604 may also be coupled with memory 655 via a bus/interconnect 651 and memory control 652. Processor core 602 and core 604 may also be coupled with graphics processing devices GFX 606 and GFX 608, and optionally other processing devices such as video device 607 and device 609 via memory 655 and bus/interconnects 615 and 651 and optionally via last level cache, LLC 616. Memory 655 and other tangible storage media of system 603 may record functional descriptive material including executable instructions to implement of a process to use a shared page miss handler for multiple processing cores or other devices to share virtual memory in a multi-core system.

Some embodiments of system 603 may adhere to industry standards which allow multiple operating systems running simultaneously within a single computer to natively share devices like Single Root I/O Virtualization (SRIOV), which provides native I/O virtualization in PCI Express topologies, or Multi-Root I/O Virtualization (MRIOV), which provides native I/O virtualization in topologies where multiple root complexes share a PCI Express hierarchy. Some embodiments of system 603 may include standard or non-standard or proprietary technologies, interfaces, busses or interconnects such as the SPI bus, USB, AMBA APB; FireWire, HDMI, Mini DisplayPort, MIPI SLIMbus, MIPI LLI, MIPI CSI, MIPI DSI, etc.

These multiple processing cores or other processing devices may share virtual memory address spaces via memory 655 and optionally through last level cache, LLC 614. Typically, the processor cores may have cache hierachies, and TLBs, e.g. TLB 622 and TLB 642, respectively to cache virtual to physical address translations from a host or guest operating system page tables in a paged virtual memory system.

The graphics processing devices, GFX 606 and GFX 608, and optionally other processing devices such as video device 607 and device 609 may also have mechanisms such as TLBs, e.g. TLB 662, TLB 682, TLB 672 and TLB 692, respectively, for performing virtual to physical address translations. Various embodiments of TLB 662, TLB 682, TLB 672 and TLB 692, respectively, may or may not have the same capabilities, or capabilities comparable to processor cores 602 and 604.

If one or more of processor cores 602 and 604, graphics processing devices GFX 606, GFX 608, and optionally video device 607 and device 609, while accessing their TLBs via a TLB lookup, generate a page miss, then they may send a page miss requests to the central PMH 610 of apparatus 601. Apparatus 601 may receive one or more page miss requests from one or more respective requesting devices of the plurality of devices, processor cores 602 and 604, graphics processing devices GFX 606, GFX 608, and optionally video device 607 and device 609, in the multi-core system. When processing a page miss request from one of the requesting devices, apparatus 601 may first arbitrate to identify which page miss request of the one or more requesting devices to process. Apparatus 601 may perform a second local TLB lookup to TLB 612 to satisfy the page miss request and upon a page miss in TLB 612, apparatus 601 may then perform a page table walk using PMH 610 to generate a physical address responsive to the first page miss request. Then the physical address may be sent by apparatus 601 to the corresponding requesting device, or a fault may be signaled by apparatus 601 to an operating system for the corresponding requesting device responsive to the first page miss request. It will be appreciated that whenever duplicate page miss requests are received by apparatus 601, if any duplicate request has been, or is being processed by PMH 610, the other duplicate requests can wait to be satisfied along with the first request. Thus duplication of page walks may be eliminated when virtual memory space is shared by more of these devices. Similarly, if the first request generates a page faul, duplicate page fault signals to the operating system may also be eliminated.

The above description is intended to illustrate preferred embodiments of the present invention. From the discussion above it should also be apparent that especially in such an area of technology, where growth is fast and further advancements are not easily foreseen, the invention may be modified in arrangement and detail by those skilled in the art without departing from the principles of the present invention within the scope of the accompanying claims and their equivalents. 

1.-20. (canceled)
 21. A system comprising: a plurality of requesting devices including a plurality of processor cores; an interconnect to couple together the plurality of processor cores; a page miss request queue to receive a page miss request for a respective miss in a translation lookaside buffer (TLB) of each of the plurality of requesting devices; arbitration logic to identify a first page miss request of a plurality of page miss requests to process; a single, shared page miss handler (PMH) to perform a page table walk to generate a physical address responsive to the first page miss request; and communication logic to send the physical address to a corresponding requesting device of the plurality of requesting devices.
 22. The system of claim 21, further comprising logic to signal a fault for the corresponding requesting device responsive to the first page miss request.
 23. The system of claim 21, further comprising a TLB coupled with the PMH to store the physical address after the page table walk.
 24. The system of claim 21, wherein the plurality of requesting devices further comprises a graphics processor.
 25. The system of claim 21, wherein the plurality of requesting devices further comprises a transport processor.
 26. The system of claim 21, wherein the plurality of requesting devices further comprises a security processor.
 27. The system of claim 21, wherein the plurality of requesting devices further comprises a video device.
 28. The system of claim 21, further comprising a connectivity device coupled to the plurality of processor cores.
 29. The system of claim 21, further comprising a serial bus coupled to the plurality of processor cores.
 30. The system of claim 21, further comprising a modem device coupled to the plurality of processor cores.
 31. The system of claim 21, further comprising a memory controller coupled to the single, shared page miss handler.
 32. The system of claim 21, further comprising an I/O expansion device coupled to the plurality of processor cores.
 33. The system of claim 21, further comprising a solid state drive coupled to the plurality of processor cores.
 34. A method comprising: executing instructions with a plurality of processor cores; coupling the plurality of processor cores together with an interconnect; receiving a page miss request in a page miss request queue for a respective miss in a translation lookaside buffer (TLB) of each of a plurality of requesting devices including the plurality of processor cores; identifying a first page miss request of a plurality of page miss requests to process; performing a page table walk with a single, shared page miss handler (PMH) to generate a physical address responsive to the first page miss request; and sending the physical address to a corresponding requesting device of the plurality of requesting devices.
 35. The method of claim 34, further comprising signaling a fault for the corresponding requesting device responsive to the first page miss request.
 36. The method of claim 34, further comprising storing the physical address after the page table walk in a TLB coupled with the PMH.
 37. The method of claim 34, wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a graphics processor of the plurality of requesting devices.
 38. The method of claim 34, wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a transport processor of the plurality of requesting devices.
 39. The method of claim 34, wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a security processor of the plurality of requesting devices.
 40. The method of claim 34, wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a video device of the plurality of requesting devices.
 41. The method of claim 34, further comprising coupling the plurality of processor cores to a connectivity device.
 42. The method of claim 34, further comprising coupling the plurality of processor cores to a serial bus.
 43. The method of claim 34, further comprising coupling the plurality of processor cores to a modem device.
 44. The method of claim 34, further comprising coupling the plurality of processor cores to a memory controller.
 45. The method of claim 34, further comprising coupling the plurality of processor cores to an I/O expansion device. 